In advanced integrated circuit (IC) packaging technologies, such as 3DIC and lead-free packaging, there are continuing trends toward higher chip density and a higher number of input/output pads. These trends have resulted in the shrinking of distances between various IC components, such as flip-chip bonded active dies and other surface mount devices (e.g., passive components) in the IC package.
As part of the IC packaging process, underfill (e.g., a polymer) may be dispensed under dies to relieve stress and provide structural support. Typically, the underfill dispensing process includes applying a plasma treatment to a package substrate and jetting underfill over the substrate under a die. The plasma treatment changes the surface properties of the substrate to be hydrophilic, allowing the underfill to flow into gaps between the die and the substrate via capillary force.
Because of variations in gap volume and underfill weight, a large fillet width may results from this process. Excess fillet width may cause various problems in the IC package, such as die edge cracking. Furthermore, issues may arise if underfill comes in contact with surface mount devices (SMDs) in the proximity of the die. For example, underfill and SMDs are formed of different materials and have different thermal coefficients of expansion. Therefore, if underfill comes in contact with a SMD, cracks and broken connections may result during subsequent thermal processes.
Furthermore, underfill applied with known processes may display an irregular fillet. That is, fillet width may be unevenly distributed and have a large standard deviation (σ). For example, underfill applied with known processes may have a fillet width 3σ value of 400 μm or more. This large standard deviation of fillet widths may necessitate the placement of limiting IC design rules on the minimum spacing required between a die and other features (e.g., SMDs) in an IC package.